Pixel array substrate and display device

ABSTRACT

A pixel array substrate includes: a first through fourth transistors (Ta through Td); a light-emitting element (OEL); a scanning line connected with a control terminal of the fourth transistor; a data line connected with one conducting terminal of the fourth transistor; a first control line (AZi) connected with one conducting terminal of the third transistor; a second control line (Ei) connected with a control terminal of the first transistor; and a first power source line (Ypj) connected with one conducting terminal of the first transistor. One conducting terminal of the second transistor is connected with the first power source line via the first transistor. A control terminal of the second transistor is connected with the data line via the fourth transistor and with a terminal of the light-emitting element via a capacitor (C).

CROSS REFERENCE TO RELATED APPLICATIONS

This is a U.S. National Phase patent application of PCT/JP2010/072395,filed Dec. 13, 2010, which claims priority to Japanese PatentApplication No. 2009-283222, filed Dec. 14, 2009, each of which ishereby incorporated by reference in the present disclosure in itsentirety.

TECHNICAL FIELD

The present invention relates to a pixel array substrate including alight-emitting element (e.g., organic EL element), and a display deviceincluding the pixel array substrate.

BACKGROUND ART

Patent Literature 1 discloses a display device including an organic ELelement (see FIG. 13). This conventional display device includes controllines DSL, AZL1, AZL2, and WSL, a signal line DTL, and power sourcelines Vofs, Vss, Vcc, and Vcat. The pixel circuit 10 is provided with anorganic EL element 1, five n-channel transistors T1 through T5, and acapacitor C1. A gate terminal of T1 is connected with WSL. A gateterminal of T2 is connected with AZL2. A gate terminal of T3 isconnected with DSL. A gate terminal of T4 is connected with AZL1. A gateterminal of T5 (drive transistor) is connected with DTL via T1 and isconnected with Vofs via T2. A drain terminal of T5 is connected with Vccvia T3. A source terminal of T5 (i) is connected with an anode of theorganic EL element and (ii) is connected with Vss via T4. A capacitor C1is provided between the gate terminal of T5 and the source terminal ofT5. A cathode of the organic EL element is connected with Vcat.

The pixel circuit 10 is configured such that, after an anode potentialof the organic EL element 1 is initialized and a threshold of the drivetransistor T5 is detected (the threshold is stored between the gateterminal of T5 and the source terminal of T5), a data signal potentialis written into the gate terminal of T5 via T1 and an electric currentis caused to flow through the organic EL element 1 via T3 and T5 (theorganic EL element 1 is caused to emit light). According to theconfiguration, it is possible to compensate for a resistance increasecaused by the threshold of the drive transistor T5 and by deteriorationof the organic EL element.

Patent Literature 1 discloses a configuration in which the power sourceline Vofs connected with T2 is integrated with the control line WSL.Patent Literature 2 discloses a configuration in which a control lineAZL2 is integrated with a control line WSL in a previous row. PatentLiterature 3 discloses a configuration in which (i) a power source lineVss connected with T4 and a power source line Vofs connected with T2 areintegrated with each other and (ii) an electrical potential to besupplied is switched every period.

CITATION LIST Patent Literature

Patent Literature 1

Japanese Patent Application Publication, Tokukai, No. 2006-215275 A(Publication Date: Aug. 17, 2006)

Patent Literature 2

Japanese Patent Application Publication, Tokukai, No. 2007-316453 A(Publication Date: Dec. 6, 2007)

Patent Literature 3

Japanese Patent Application Publication, Tokukai, No. 2007-108380 A(Publication Date: Apr. 26, 2007)

SUMMARY OF INVENTION Technical Problem

However, the configuration of the pixel circuit illustrated in FIG. 13has a problem of having many power source lines (four systems of Vofs,Vss, Vcc, and Vcat are necessary). In addition, at the time ofinitializing the anode potential of the organic EL element, an electriccurrent path is formed along the following route: the power source lineVcc→T3→T5→T4→the power source line Vss. In a case where transistorsoperate in a linear region, a large electric current undesirably flowsthrough the electric current path.

An object of the present invention is to realize a pixel array substratehaving a small number of power source lines.

Solution to Problem

A pixel array substrate of the present invention includes: a firstthrough fourth transistors; a light-emitting element; a first powersource line connected with one conducting terminal of the firsttransistor; a first control line connected with one conducting terminalof the third transistor; a second control line connected with a controlterminal of the first transistor; a scanning line connected with acontrol terminal of the fourth transistor; and a data line connectedwith one conducting terminal of the fourth transistor, one conductingterminal of the second transistor being connected with the first powersource line via the first transistor, a control terminal of the secondtransistor being connected with the data line via the fourth transistorand being connected with a terminal of the light-emitting element via acapacitor, the terminal of the light-emitting element, the otherconducting terminal of the second transistor, the other conductingterminal of the third transistor, and a control terminal of the thirdtransistor being connected with one another.

The pixel array substrate of the present invention is, for example,driven in the following manner. First, a terminal potential of thelight-emitting element is initialized by (i) turning on the firsttransistor and (ii), while a predetermined electric potential issupplied to the control terminal of the second transistor, turning onthe third transistor under a condition which allows no electric currentto flow through the light-emitting element. Next, a threshold of thesecond transistor is detected by (i) turning off the third transistorand (ii) subsequently, while the predetermined electric potential keepsbeing supplied to the control terminal of the second transistor, turningthe second transistor from an on-state to an off-state under a conditionwhich allows no electric current to flow through the light-emittingelement. Next, a data signal potential is written from the data lineinto the control terminal of the second transistor via the fourthtransistor after the first transistor is turned off. Subsequently, thefirst transistor is turned on, so that an electric current is caused toflow from the first power source line to the light-emitting element, viathe first transistor and the second transistor (the light-emittingelement is caused to emit light).

As describe above, since the third transistor is provided in a diodeconnection configuration in the pixel array substrate of the presentinvention, the number of power source lines can be reduced as comparedwith a conventional configuration (see FIG. 13). This makes it possibleto enhance an aperture ratio and reduce a parasitic capacitance betweena power source line and wiring (e.g., a data line) which intersects thepower source line. In addition, the power source line and the wiringthat intersects the power source line are short-circuited less often.This increases yields (productivity). Further, since it is onlynecessary that a gate terminal and a drain terminal of the same elementbe short-circuited (connected), arrangement of wiring in a pixel circuitis facilitated and a layout area can be reduced. Further, it becomespossible to reduce external power source circuits which supply a powersource potential to the pixel array substrate of the present invention.

Further, with respect to the third transistor, the following equation ismet: [a voltage between (i) the conducting terminal connected with thelight-emitting element and (ii) the control terminal]=[a voltage betweenthe two conducting terminals]. As such, the third transistor alwaysoperates in a saturation region. Therefore, unlike in the conventionalconfiguration (see FIG. 13), a large electric current does not flow atthe time of initializing the terminal potential of the light-emittingelement. This realizes an electric current limiter function.

Advantageous Effects of Invention

As described above, according to the present invention, it is possibleto realize a pixel array substrate having a small number of power sourcelines.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a displaydevice in accordance with Embodiment 1.

FIG. 2 is a circuit diagram illustrating a partial configuration (4pixels) of a pixel array in accordance with Embodiment 1.

FIG. 3 is a timing chart showing a method for driving the pixel arrayillustrated in FIG. 2.

FIG. 4 is a circuit diagram for describing an effect of the pixel arrayillustrated in FIG. 2.

FIG. 5 is a block diagram illustrating a configuration of a displaydevice in accordance with Embodiment 2.

FIG. 6 is a circuit diagram illustrating a partial configuration (fourpixels) of a pixel array in accordance with Embodiment 2.

FIG. 7 is a timing chart showing a method for driving the pixel arrayillustrated in FIG. 6.

FIG. 8 is a block diagram illustrating a configuration of a displaydevice in accordance with Embodiment 3.

FIG. 9 is a circuit diagram illustrating a partial configuration (fourpixels) of a pixel array in accordance with Embodiment 3.

FIG. 10 is a timing chart showing a method for driving a pixel arrayillustrated in FIG. 9.

FIG. 11 is a circuit diagram illustrating a partial configuration (fourpixels) of a pixel array in accordance with Embodiment 4.

FIG. 12 is a timing chart showing a method for driving a pixel arrayillustrated in FIG. 11.

FIG. 13 is a pixel circuit diagram of a conventional display device.

DESCRIPTION OF EMBODIMENTS

The following description will discuss an embodiment of the presentinvention with reference to FIGS. 1 through 12.

Embodiment 1

FIG. 1 is a block diagram illustrating a configuration of a displaydevice of the present embodiment. As illustrated in FIG. 1, the displaydevice of the present embodiment includes a pixel array substrate PAS, adisplay control circuit DCC, a first driver DR1, and a second driverDR2. On the pixel array substrate PAS, (i) a first power source line Ypjand a data line Sj are provided for, for example, a j-th pixel columnand (ii) a first control line AZi, a second control line Ei, a scanningline Gi, a third control line Ri, and a second power source line Xpi areprovided for, for example, an i-th pixel row. The first driver DR1drives the first power source line Ypj and the data line Sj on the basisof a clock signal CK and a start pulse SP which are supplied from thedisplay control circuit DCC. The second driver DR2 drives the firstcontrol line AZi, the second control line Ei, the scanning line Gi, thethird control line Ri, and the second power source line Xpi on the basisof a clock signal CK, video data DA, and a start pulse SP which aresupplied from the display control circuit DCC.

A partial configuration (four pixel circuits) of a pixel array substratein accordance with Embodiment 1 is illustrated in FIG. 2. As illustratedin FIG. 2, an organic EL element (organic light-emitting diode,light-emitting element) OEL, five n-channel transistors Ta through Te(first through fifth transistors), and a capacitor C are provided in apixel circuit Pij belonging to the i-th pixel row and the j-th pixelcolumn.

A gate terminal of Ta is connected with the second control line Ei. Agate terminal of Td is connected with the scanning line Gi. A gateterminal of Te is connected with the third control line Ri. A gateterminal of Tb (drive transistor) is connected with the data line Sj viaTd and is connected with the second power source line Xpi via Te. Adrain terminal of Tb is connected with the first power source line Ypjvia Ta. A drain terminal of Te is connected with the second power sourceline Xpi. The capacitor C is provided between the gate terminal of Tband a source terminal of Tb. The source terminal of Tb is connected withan anode of the organic EL element OEL and is connected, via Tc, withthe first control line AZi. A cathode of the organic EL element OEL isconnected with Vcom. A gate terminal of Tc and a drain terminal of Tcare connected with each other. That is, in a pixel circuit of thepresent embodiment, (i) the gate terminal of the transistor Tc and thedrain terminal of the transistor Tc are connected with the anode of theorganic EL element OEL and (ii) a source terminal of the transistor Tcis connected with the first control line AZi.

FIG. 3 shows a method for driving the pixel circuit Pij in the pixelarray substrate PAS having the pixel circuits illustrated in FIG. 2. InFIG. 3, (i) AZi represents an electric potential of the first controlline AZi, (ii) Ri represents an electric potential of the third controlline Ri, (iii) Ei represents an electric potential of the second controlline Ei, (iv) Gi represents an electric potential of the scanning lineGi, (v) Sj represents an electric potential of the data line Sj, (vi)Xpi presents an electric potential of the second power source line Xpi,(vii) Vg(Tb) represents a gate potential of the transistor Tb, and(viii) Vs(Tb) represents a source potential of the transistor Tb.

As shown in FIG. 3, at t1, when the electric potential of the secondcontrol line Ei is “High”, (i) the electric potential of the firstcontrol line AZi changes from “High” to “Low” and (ii) the electricpotential of the third control line Ri changes from “Low” to “High”, sothat a period A, in which an anode potential of the organic EL elementOEL is reset, begins. In the period A, the transistor Te is in anon-state and the gate potential Vg(Tb) of the transistor (drivetransistor) Tb becomes an electric potential of the second power sourceline Xpi.

Note that Vref, which is an electric potential of the second powersource line Xpi, and VL(AZ), which is a “Low” electric potential of thefirst control line AZi, are set so that the following formulae (1)through (3) are met where Vth(Tb) is a threshold potential of thetransistor Tb, Vth(Tc) is a threshold potential of the transistor Tc,and Vth(EL) is a light emission threshold of the organic EL element OEL.VL(AZ)<Vth(EL)−Vth(Tc)  (1)Vref>Vth(Tb)+VL(AZ)+Vth(Tc)  (2)Vref<Vth(EL)+Vth(Tb)  (3)

Therefore, in the period A, an electric current flows from the anode ofthe organic EL element OEL to the first control line AZi via thetransistor Tc, but no electric current flows through the organic ELelement OEL according to the Formula (1). Because of this, the anodepotential of the organic EL element OEL (which anode potential is equalto the source potential of the transistor Tb) is initialized intoVL(AZ)+Vth(Tc). At this time, the transistor Tb is in an on-stateaccording to the Formula (2), but no electric current flows through theorganic EL element OEL according to Formula (3). Note that an aspectratio (W/L ratio) of the transistor Tc is preferably smaller than anaspect ratio (W/L ratio) of the transistor Tb. When the anode potentialof the organic EL element OEL is initialized, an electric current flowsin the following path: the first power source line Ypj→Ta→Tb→Tc→thefirst control line AZi. By setting the aspect ratio of Tc to be smallerthan the aspect ratio of Tb, it is possible to reduce an electriccurrent that flows through Tb, which has the biggest impact on displayquality in a case where differences in characteristic exist (reduceelectric current stress on Tb). This makes it possible to reduce changesin the characteristic of Tb.

When the electric potential of the first control line AZi changes from“Low” to “High” at t2, the period A ends and a period B, in which athreshold of the transistor Tb is detected, begins. In the period B, thesource potential of the transistor Tc increases so that the transistorTc is turned off, but no electric current flows through the organic ELelement OEL according to the Formula (1). This causes the anodepotential of the organic EL element OEL (which anode potential is equalto the source potential of the transistor Tb) to increase. When thesource potential Vs(Tb) of the transistor Tb becomes equal toVref−Vth(Tb), the transistor Tb is turned off. Note that the transistorTc is preferably an enhancement-type transistor having a positive(higher than a ground potential) threshold, in order that the transistorTc is reliably turned off in the period B (other than the period A).

When the electric potential of the second control line Ei changes from“High” to “Low” at t3, the period B ends and the transistor Ta is turnedoff. Subsequently at t4, the electric potential of the third controlline Ri changes from “High” to “Low” and the transistor Te is alsoturned off.

When the electric potential of the scanning line Gi changes from “Low”to “High” at t5, a period C, which is a data writing period, begins. Inthe period C, a data signal potential Vdat is written, from the dataline Sj, into the gate terminal of the transistor Tb, so that Vg(Tb)becomes equal to Vdat. At this time, the following formula is met whereVgs is a voltage between the gate terminal of the transistor Tb and thesource terminal of the transistor Tb, Cst is a capacitance between thegate terminal of the transistor Tb and the source terminal of thetransistor Tb, and Cel is a capacitance of the organic EL element OEL.Vgs={Cel/(Cel+Cst)}×(Vdat−Vref)+Vth(Tb)However, since Cel is far larger than Cst, the following formula is met.Vgs=Vdat−Vref+Vth(Tb)  (4)Thus, the voltage Vgs between the gate terminal of the transistor Tb andthe source terminal of the transistor Tb has a value that is determinedin accordance with data.

When the electric potential of the scanning line Gi changes from “High”to “Low” at t6, the period C ends. Subsequently, when the electricpotential of the second control line Ei changes from “Low” to “High” att7, a period D, in which the organic EL element OEL emits light, begins.In the period D, an electric current flows from the first power sourceline Ypj to the organic EL element OEL via the transistors Ta and Tb, inaccordance with Vgs (the voltage between the gate terminal of thetransistor Tb and the source terminal of the transistor Tb). At thistime, since the gate terminal of the transistor Tb electrically floats,the gate potential of the transistor Tb increases as the sourcepotential of the transistor Tb increases. This allows Vgs to bemaintained substantially constant. Note that it is possible to ignore achannel length modulation effect by setting an electric potential of afirst power source line Yp so that the transistor Tb operates in asaturation region. A drain current Ib of the transistor Tb can beexpressed by the following formula where L is a channel length, W is achannel width, p is electron mobility, and Cox is a capacitance of anoxide.Ib={W×μ×Cox×(Vgs−Vth(Tb))²}/(2×L)From Formula (4), the drain current Ib can be expressed by the followingformula.Ib={W×μ×Cox×(Vdat−Vref)²}/(2×L)

That is, the drain current Ib (an electric current flowing through theorganic EL element OEL) can be set to a value in accordance with Vdat,irrespective of (i) differences in threshold Vth(Tb) among pixelcircuits and (ii) a change in Vth(Tb) over time.

As describe above, since the transistor Tc is provided in a diodeconnection configuration in the pixel array substrate of the presentembodiment, the number of power source lines can be reduced as comparedwith a conventional configuration (see FIG. 13). This makes it possibleto enhance an aperture ratio and reduce a parasitic capacitance betweena power source line and wiring (e.g., a data line) which intersects thepower source line. In addition, the power source line and the wiringthat intersects the power source line are short-circuited less often.This increases yields (productivity). Further, since it is onlynecessary that a gate terminal and a drain terminal of the same elementbe short-circuited (connected), arrangement of wiring in a pixel circuitis facilitated and a layout area can be reduced. Further, it becomespossible to reduce external power source circuits which supply a powersource potential to the pixel array substrate of the present embodiment.

In addition, an advantageous effect in terms of driving can also beexpected as follows. In the period A (the period in which the anodepotential of the organic EL element OEL is reset), an electric currentpath is formed from the first power source line Yp to the first controlline AZi, as indicated by the dotted arrow in FIG. 4. At this time,according to the pixel array substrate of the present embodiment, avoltage vgs between the gate terminal of and the source terminal of thetransistor Tc is equal to a voltage vds between the drain terminal ofand the source terminal of the transistor Tc, so that the transistor Tcalways operates in a saturation region. In the saturation region, adrain current Ic of the transistor Tc is limited by the followingformula.Ic={W×μ×Cox×(vgs−Vth(Tc))²}/(2×L)As such, a large electric current does not flow unlike in theconventional configuration (see FIG. 13). That is, according to thepixel array substrate of the present embodiment, an electric currentlimiter function at the time of initializing an anode potential is alsoachieved.

Embodiment 2

FIG. 5 is a block diagram illustrating a display device of the presentembodiment. As illustrated in FIG. 5, the display device of the presentembodiment includes a pixel array substrate PAS, a display controlcircuit DCC, a first driver DR1, and a second driver DR2. On the pixelarray substrate PAS, (i) a first power source line Ypj and a data lineSj are provided for, for example, a j-th pixel column and (ii) a firstcontrol line AZi, a second control line Ei, a scanning line Gi, and athird control line Ri are provided for, for example, an i-th pixel row.The first driver DR1 drives the first power source line Ypj and the dataline Sj on the basis of a clock signal CK and a start pulse SP which aresupplied from the display control circuit DCC. The second driver DR2drives the first control line AZi, the second control line Ei, thescanning line Gi, and the third control line Ri, on the basis of a clocksignal CK, video data DA, and a start pulse SP which are supplied fromthe display control circuit DCC.

A partial configuration (four pixel circuits) of a pixel array substratein accordance with Embodiment 2 is illustrated in FIG. 6. As illustratedin FIG. 6, an organic EL element OEL, five n-channel transistors(field-effect transistors) Ta through Te, and a capacitor C are providedin a pixel circuit Pij belonging to the i-th pixel row and the j-thpixel column.

A gate terminal of Ta is connected with the second control line Ei. Agate terminal of Td is connected with the scanning line Gi. A gateterminal of Te is connected with the third control line Ri. A gateterminal of Tb (drive transistor) is connected with the data line Sj viaTd and is connected with the second power source line Xpi via Te. Adrain terminal of Tb is connected with the first power source line Ypjvia Ta. A drain terminal of Te is connected with the scanning line Gi.The capacitor C is provided between the gate terminal of Tb and a sourceterminal of Tb. The source terminal of Tb is connected with an anode ofthe organic EL element OEL and is connected, via Tc, with the firstcontrol line AZi. A cathode of the organic EL element OEL is connectedwith Vcom. A gate terminal of Tc and a drain terminal of Tc areconnected with each other. That is, in a pixel circuit of the presentembodiment, (i) the gate terminal of the transistor Tc and the drainterminal of the transistor Tc are connected with the anode of theorganic EL element OEL and (ii) a source terminal of the transistor Tcis connected with the first control line AZi.

FIG. 7 shows a method for driving the pixel circuit Pij in the pixelarray substrate PAS having the pixel circuits illustrated in FIG. 6. InFIG. 7, (i) AZi represents an electric potential of the first controlline AZi, (ii) Ri represents an electric potential of the third controlline Ri, (iii) Ei represents an electric potential of the second controlline Ei, (iv) Gi represents an electric potential of the scanning lineGi, (v) Sj represents an electric potential of the data line Sj, (vi)Vg(Tb) represents a gate potential of the transistor Tb, and (vii)Vs(Tb) represents a source potential of the transistor Tb.

FIG. 7 shows the method for driving the pixel circuit Pij in the pixelarray substrate PAS having the pixel circuits illustrated in FIG. 6. InFIG. 7, (i) AZi represents the electric potential of the first controlline AZi, (ii) Ri represents the electric potential of the third controlline Ri, (iii) Ei represents the electric potential of the secondcontrol line Ei, (iv) Gi represents the electric potential of thescanning line Gi, (v) Sj represents the electric potential of the dataline Sj, (vi) Vg(Tb) represents the gate potential of the transistor Tb,and (vii) Vs(Tb) represents the source potential of the transistor Tb.

The configuration illustrated in FIG. 6 is obtained by integrating thesecond power source line Xpi and the scanning line Gi which areillustrated in FIG. 2. As such, VL(Gi), which is a “Low (inactive)”electric potential of the scanning line Gi and VL(AZ), which is a “Low”electric potential of the first control line AZi, are set so that thefollowing formulae (5) through (7) are met where Vth(Tb) is a thresholdpotential of the transistor Tb, Vth(Tc) is a threshold potential of thetransistor Tc, and Vth(EL) is a light emission threshold of the organicEL element OEL.VL(AZ)<Vth(EL)−Vth(Tc)  (5)VL(Gi)>Vth(Tb)+VL(AZ)+Vth(Tc)  (6)VL(Gi)<Vth(EL)+Vth(Tb)  (7)

Note that operations in the respective periods A through D are the sameas described above with reference to FIG. 3.

The pixel array substrate of Embodiment 2 has a merit of being able toreduce further the number of power source lines, in addition to themerits as described in Embodiment 1. This makes it possible to increasean aperture ratio and reduce a parasitic capacitance between a powersource line and wiring (e.g., a data line) which intersects the powersource line. In addition, the power source line and the wiring thatintersects the power source line are short-circuited less often. Thisincreases yields (productivity). Further, it becomes possible to reduceexternal power source circuits which supply a power source potential tothe pixel array substrate.

Embodiment 3

FIG. 8 is a block diagram illustrating a configuration of a displaydevice of the present embodiment. As illustrated in FIG. 8, the displaydevice of the present embodiment includes a pixel array substrate PAS, adisplay control circuit DCC, a first driver DR1, and a second driverDR2. On the pixel array substrate PAS, (i) a first power source line Ypjand a data line Sj are provided for, for example, a j-th pixel columnand (ii) a first control line AZi, a second control line Ei, and ascanning line Gi are provide for, for example, an i-th pixel row. Thefirst driver DR1 drives the first power source line Ypj and the dataline Sj on the basis of a clock signal CK and a start pulse SP which aresupplied from the display control circuit DCC. The second driver DR2drives the first control line AZi, the second control line Ei, and thescanning line Gi on the basis of a clock signal CK, video data DA, and astart pulse SP which are supplied from the display control circuit DCC.

A partial configuration (four pixel circuits) of a pixel array substratein accordance with Embodiment 3 is illustrated in FIG. 9. As illustratedin FIG. 9, an organic EL element OEL, five n-channel transistors Tathrough Te, and a capacitor C are provided in a pixel circuit Pijbelonging to the i-th pixel row and the j-th pixel column.

A gate terminal of Ta is connected with the second control line Ei. Agate terminal of Td is connected with the scanning line Gi in the i-thpixel row. A gate terminal of Te is connected with a scanning signalline G(i-1) in the (i-1)-th pixel row. A gate terminal of Tb (drivetransistor) is connected with the data line Sj via Td and is connectedwith the second power source line Xpi via Te. A drain terminal of Tb isconnected with the first power source line Ypj via Ta. A drain terminalof Te is connected with the scanning line Gi in the i-th pixel row. Thecapacitor C is provided between the gate terminal of Tb and a sourceterminal of Tb. The source terminal of Tb is connected with an anode ofthe organic EL element OEL and is connected, via Tc, with the firstcontrol line AZi. A cathode of the organic EL element OEL is connectedwith Vcom. A gate terminal of Tc and a drain terminal of Tc areconnected with each other. That is, in a pixel circuit of the presentembodiment, (i) the gate terminal of the transistor Tc and the drainterminal of the transistor Tc are connected with the anode of theorganic EL element OEL and (ii) a source terminal of the transistor Tcis connected with the first control line AZi.

FIG. 10 shows a method for driving the pixel circuit Pij in the pixelarray substrate PAS having the pixel circuits illustrated in FIG. 9. InFIG. 10, (i) AZ(i-1) represents an electric potential of a first controlline AZ(i-1) in the (i-1)-th pixel row, (ii) E(i-1) represents anelectric potential of a second control line E(i-1) in the (i-1)-th pixelrow, (iii) G(i-1) represents an electric potential of a scanning lineG(i-1) in the (i-1)-th pixel row, (iv) AZi represents an electricpotential of the first control line AZi in the i-th pixel row, (v) Eirepresents an electric potential of the second control line Ei in thei-th pixel row, (vi) Gi represents an electric potential of the scanningline Gi in the i-th pixel row, (vii) Sj represents an electric potentialof the data line Sj, (viii) Vg(Tb) represents a gate potential of thetransistor Tb, and (ix) Vs(Tb) represents a source potential of thetransistor Tb.

As shown in FIG. 10, at t1, when the electric potential of the secondcontrol line Ei is “High”, (i) the electric potential of the firstcontrol line AZi changes from “High” to “Low” and (ii) the electricpotential of the scanning line G(i-1) in the (i-1)-th pixel row changesfrom “Low” to “High”, so that a period A, in which an anode potential ofthe organic EL element OEL is reset, begins. In the period A, thetransistor Te is in an on-state and the gate potential Vg(Tb) of thetransistor (drive transistor) Tb becomes an electric potential of thesecond power source line Xpi.

Note that VL(Gi), which is a “Low (inactive)” electric potential of thescanning line Gi, and VL(AZ), which is a “Low” electric potential of thefirst control line AZi, are set so that the formulae (5) through (7)described in Embodiment 2 are met where Vth(Tb) is a threshold potentialof the transistor Tb, Vth(Tc) is a threshold potential of the transistorTc, and Vth(EL) is a light emission threshold of the organic EL elementOEL.

Therefore, in the period A, an electric current flows from the anode ofthe organic EL element OEL to the first control line AZi via thetransistor Tc, but no electric current flows through the organic ELelement OEL according to the Formula (5). Because of this, the anodepotential of the organic EL element OEL (which anode potential is equalto the source potential of the transistor Tb) is initialized intoVL(AZ)+Vth(Tc). At this time, the transistor Tb is in an on-stateaccording to the Formula (6), but no electric current flows through theorganic EL element OEL according to Formula (7).

When the electric potential of the first control line AZi changes from“Low” to “High” at t2, the period A ends and a period B, in which athreshold of the transistor Tb is detected, begins. In the period B, thesource potential of the transistor Tc increases so that the transistorTc is turned off, but no electric current flows through the organic ELelement OEL according to the Formula (8). This causes the anodepotential of the organic EL element OEL (which anode potential is equalto the source potential of the transistor Tb) to increase. When thesource potential Vs(Tb) of the transistor Tb becomes equal toVref−Vth(Tb), the transistor Tb is turned off.

When the electric potential of the second control line Ei changes from“High” to “Low” at t3, the period B ends and the transistor Ta is turnedoff. Subsequently at t4, the electric potential of the scanning lineG(i-1) in the (i-1)-th pixel row changes from “High” to “Low” and thetransistor Te is also turned off.

Operations in the respective periods C and D are the same as describedabove with reference to FIG. 3.

The pixel array substrate of Embodiment 3 has a merit of being able toreduce further the number of control lines, in addition to the merits asdescribed in Embodiment 2. This makes it possible to increase anaperture ratio and reduce a parasitic capacitance between a control lineand wiring (e.g., a data line) which intersects the control line. Inaddition, the control line and the wiring that intersects the controlline are short-circuited less often. This increases yields(productivity). Further, it becomes possible to simplify a configurationof the second driver DR2 which drives control lines.

Embodiment 4

A display device in accordance with Embodiment 4 has the sameconfiguration as the configuration illustrated in FIG. 8. A partialconfiguration (four pixel circuits) of a pixel array substrate inaccordance with Embodiment 4 is illustrated in FIG. 11. As illustratedin FIG. 11, an organic EL element OEL, four n-channel transistors Tathrough Td, and a capacitor C are provided in a pixel circuit Pijbelonging to the i-th pixel row and the j-th pixel column.

A gate terminal of Ta is connected with the second control line Ei. Agate terminal of Td is connected with the scanning line Gi in the i-thpixel row. A gate terminal of Tb (drive transistor) is connected withthe data line Sj via Td. A drain terminal of Tb is connected with thefirst power source line Ypj via Ta. The capacitor C is provided betweenthe gate terminal of Tb and a source terminal of Tb. The source terminalof Tb is connected with an anode of the organic EL element OEL and isconnected, via Tc, with the first control line AZi. A cathode of theorganic EL element OEL is connected with Vcom. A gate terminal of Tc anda drain terminal of Tc are connected with each other. That is, in apixel circuit of the present embodiment, (i) the gate terminal of thetransistor Tc and the drain terminal of the transistor Tc are connectedwith the anode of the organic EL element OEL and (ii) a source terminalof the transistor Tc is connected with the first control line AZi.

FIG. 12 shows a method for driving the pixel circuit Pij in the pixelarray substrate PAS having the pixel circuits illustrated in FIG. 11. InFIG. 12, (i) AZi represents an electric potential of the first controlline AZi, (ii) Ei represents an electric potential of the second controlline Ei, (iii) Gi represents an electric potential of the scanning lineGi, (iv) Sj represents an electric potential of the data line Sj, (v)Vg(Tb) represents a gate potential of the transistor Tb, and (vi) Vs(Tb)represents a source potential of the transistor Tb.

As shown in FIG. 12, at t1, when the electric potential of the secondcontrol line Ei is “High”, (i) the electric potential of the firstcontrol line AZi changes from “High” to “Low” and (ii) the electricpotential of the scanning line Gi changes from “Low” to “High”, so thata period A, in which an anode potential of the organic EL element OEL isreset, begins. In the period A, a reset potential Vref is supplied tothe data line Sj and the gate potential of Vg(Tb) of the transistor(drive transistor) Tb becomes the reset potential Vref.

Note that VL(AZ), which is the reset potential Vref and a “Low” electricpotential of the first control line AZi, is set so that the Formulae (1)through (3) described in Embodiment 1 are met.

When the electric potential of the first control line AZi changes from“Low” to “High” at t2, the period A ends and a period B, in which athreshold of the transistor Tb is detected, begins. Note that theelectric potential of the scanning line Gi remains “High”. In the periodB, the source potential of the transistor Tc increases so that thetransistor Tc is turned off, but no electric current flows through theorganic EL element OEL according to the Formula (1). This causes theanode potential of the organic EL element OEL (which anode potential isequal to the source potential of the transistor Tb) to increase. Whenthe source potential Vs(Tb) of the transistor Tb becomes equal toVref−Vth(Tb), the transistor Tb is turned off.

When the electric potential of the second control line Ei changes from“High” to “Low” at t3, the period B ends and the transistor Ta is turnedoff.

At t5, the electric potential of the scanning line Gi remains “High” anda period C, which is a data writing period, begins. In the period C, adata signal potential Vdat is written, from the data line Sj, into thegate terminal of the transistor Tb, so Vg(Tb) becomes equal to Vdat.Note that an operation in the period D is the same as described abovewith reference to FIG. 3.

The pixel array substrate of Embodiment 4 has a merit of being able toreduce the number of power source lines and the number of control lines,in addition to the merits as described in Embodiment 1. This makes itpossible to increase an aperture ratio and reduce a parasiticcapacitance between a power source line and wiring (e.g., a data line)which intersects the power source line. In addition, the power sourceline and the wiring that intersects the power source line areshort-circuited less often. This increases yields (productivity).Similarly, it becomes possible to reduce a parasitic capacitance betweena control line and wiring (e.g., a data line) which intersects thecontrol line. In addition, the control line and the wiring thatintersects the control line are short-circuited less often. Thisincreases yields (productivity). Further, it becomes possible tosimplify a configuration of the second driver DR2 which drives powersource lines and control lines. Therefore, the pixel array substrate ofEmbodiment 4 is suitable for a small-sized high-resolution display.

The present invention is not limited to the above-described embodiments.An embodiment obtained by appropriately modifying the embodiments on thebasis of common technical knowledge and an embodiment obtained bycombining modified embodiments will also be included in the embodimentsof the present invention.

A pixel array substrate of the present invention includes: a firstthrough fourth transistors; a light-emitting element; a first powersource line connected with one conducting terminal of the firsttransistor; a first control line connected with one conducting terminalof the third transistor; a second control line connected with a controlterminal of the first transistor; a scanning line connected with acontrol terminal of the fourth transistor; and a data line connectedwith one conducting terminal of the fourth transistor, one conductingterminal of the second transistor being connected with the first powersource line via the first transistor, a control terminal of the secondtransistor being connected with the data line via the fourth transistorand being connected with a terminal of the light-emitting element via acapacitor, the terminal of the light-emitting element, the otherconducting terminal of the second transistor, the other conductingterminal of the third transistor, and a control terminal of the thirdtransistor being connected with one another.

The pixel array substrate of the present invention is, for example,driven in the following manner. First, a terminal potential of thelight-emitting element is initialized by (i) turning on the firsttransistor and (ii), while a predetermined electric potential issupplied to the control terminal of the second transistor, turning onthe third transistor under a condition which allows no electric currentto flow through the light-emitting element. Next, a threshold of thesecond transistor is detected by (i) turning off the third transistorand (ii) subsequently, while the predetermined electric potential keepsbeing supplied to the control terminal of the second transistor, turningthe second transistor from an on-state to an off-state under a conditionwhich allows no electric current to flow through the light-emittingelement. Next, a data signal potential is written from the data lineinto the control terminal of the second transistor via the fourthtransistor after the first transistor is turned off. Subsequently, thefirst transistor is turned on, so that an electric current is caused toflow from the first power source line to the light-emitting element, viathe first transistor and the second transistor (the light-emittingelement is caused to emit light).

As describe above, since the third transistor is provided in a diodeconnection configuration in the pixel array substrate of the presentinvention, the number of power source lines can be reduced as comparedwith a conventional configuration (see FIG. 13). This makes it possibleto enhance an aperture ratio and reduce a parasitic capacitance betweena power source line and wiring (e.g., a data line) which intersects thepower source line. In addition, the power source line and the wiringthat intersects the power source line are short-circuited less often.This increases yields (productivity). Further, since it is onlynecessary that a gate terminal and a drain terminal of the same elementbe short-circuited (connected), arrangement of wiring in a pixel circuitis facilitated and a layout area can be reduced. Further, it becomespossible to reduce external power source circuits which supply a powersource potential to the pixel array substrate of the present invention.

Further, with respect to the third transistor, the following equation ismet: [a voltage between (i) the conducting terminal connected with thelight-emitting element and (ii) the control terminal connected with thelight-emitting element]=[a voltage between the two conductingterminals]. As such, the third transistor always operates in asaturation region. Therefore, unlike in the conventional configuration(see FIG. 13), a large electric current does not flow at the time ofinitializing the terminal potential of the light-emitting element. Thisrealizes an electric current limiter function.

The pixel array substrate of the present invention can have aconfiguration in which each of the first through fourth transistors isan n-channel field-effect transistor.

The pixel array substrate of the present invention can have aconfiguration in which the third transistor is an enhancement-typefield-effect transistor having a threshold higher than a groundpotential.

The pixel array substrate of the present invention can further include afifth transistor having one conducting terminal thereof connected withthe control terminal of the second transistor.

The pixel array substrate of the present invention can further include:a second power source line connected with the other conducting terminalof the fifth transistor; and a third control line connected with acontrol terminal of the fifth transistor.

The pixel array substrate of the present invention can further include athird control line connected with a control terminal of the fifthtransistor, the other conducting terminal of the fifth transistor beingconnected with the scanning line.

The pixel array substrate of the present invention can have aconfiguration in which the other conducting terminal of the fifthtransistor is connected with the scanning line and a control terminal ofthe fifth transistor is connected with another scanning line in apreceding stage.

The pixel array substrate of the present invention can have aconfiguration in which the light-emitting element is an organiclight-emitting diode.

The pixel array substrate of the present invention can have aconfiguration in which the third transistor has an aspect ratio smallerthan that of the second transistor.

A display device of the present invention includes the pixel arraysubstrate.

The display device of the present invention can have a configuration inwhich a terminal potential of the light-emitting element is initializedby (i) turning on the first transistor and (ii), while a predeterminedelectric potential is supplied to the control terminal of the secondtransistor, turning on the third transistor under a condition whichallows no electric current to flow through the light-emitting element.

The display device of the present invention can have a configuration inwhich the third transistor is always in an off-state except in a periodin which the terminal potential of the light-emitting element isinitialized.

The display device of the present invention can have a configuration inwhich a threshold of the second transistor is detected by (i)initializing the terminal potential of the light-emitting element andturning off the third transistor and (ii) subsequently, while thepredetermined electric potential keeps being supplied to the controlterminal of the second transistor, turning the second transistor from anon-state to an off-state under a condition which allows no electriccurrent to flow through the light-emitting element.

The display device of the present invention can have a configuration inwhich a data signal potential is written from the data line into thecontrol terminal of the second transistor via the fourth transistor,after (i) the threshold of the second transistor is detected and (ii)the first transistor is turned off.

The display device of the present invention can have a configuration inwhich, after the data signal potential is written into the controlterminal of the second transistor, the first transistor is turned on, sothat an electric current is caused to flow from the first power sourceline to the light-emitting element, via the first transistor and thesecond transistor.

INDUSTRIAL APPLICABILITY

The pixel array substrate of the present invention and the displaydevice of the present invention is suitable, for example, for an organicEL display.

REFERENCE SIGNS LIST

-   OEL: organic EL element (organic light-emitting diode)-   Ta through Te: transistors (first through fifth transistors)-   C: capacitor-   Gi: scanning line-   Sj: data line-   Ypj: first power source line-   Xpi: second power source line-   AZi: first control line-   Ei: second control line-   Ri: third control line

The invention claimed is:
 1. A pixel array substrate comprising: a firstthrough fourth transistors; a light-emitting element; a first powersource line connected with one conducting terminal of the firsttransistor; a first control line connected with one conducting terminalof the third transistor; a second control line connected with a controlterminal of the first transistor; a scanning line connected with acontrol terminal of the fourth transistor; and a data line connectedwith one conducting terminal of the fourth transistor, one conductingterminal of the second transistor being connected with the first powersource line via the first transistor, a control terminal of the secondtransistor being connected with the data line via the fourth transistorand being connected with a terminal of the light-emitting element via acapacitor, the terminal of the light-emitting element, the otherconducting terminal of the second transistor, the other conductingterminal of the third transistor, and a control terminal of the thirdtransistor being connected with one another.
 2. The pixel arraysubstrate as set forth in claim 1, wherein each of the first throughfourth transistors is an n-channel field-effect transistor.
 3. The pixelarray substrate as set forth in claim 1, wherein the third transistor isan enhancement-type field-effect transistor having a threshold higherthan a ground potential.
 4. A pixel array substrate as set forth inclaim 1, further comprising a fifth transistor having one conductingterminal thereof connected with the control terminal of the secondtransistor.
 5. A pixel array substrate as set forth in claim 4, furthercomprising: a second power source line connected with the otherconducting terminal of the fifth transistor; and a third control lineconnected with a control terminal of the fifth transistor.
 6. A pixelarray substrate as set forth in claim 4, further comprising a thirdcontrol line connected with a control terminal of the fifth transistor,the other conducting terminal of the fifth transistor being connectedwith the scanning line.
 7. The pixel array substrate as set forth inclaim 4, wherein the other conducting terminal of the fifth transistoris connected with the scanning line and a control terminal of the fifthtransistor is connected with another scanning line in a preceding stage.8. The pixel array substrate as set forth in claim 1, wherein the thirdtransistor has an aspect ratio smaller than that of the secondtransistor.
 9. The pixel array substrate as set forth in any one ofclaim 1, wherein the light-emitting element is an organic light-emittingdiode.
 10. A display device comprising a pixel array substrate recitedin claim
 1. 11. The display device as set forth in claim 10, wherein aterminal potential of the light-emitting element is initialized by (i)turning on the first transistor and (ii), while a predetermined electricpotential is supplied to the control terminal of the second transistor,turning on the third transistor under a condition which allows noelectric current to flow through the light-emitting element.
 12. Thedisplay device as set forth in claim 11, wherein the third transistor isalways in an off-state except in a period in which the terminalpotential of the light-emitting element is initialized.
 13. The displaydevice as set forth in claim 12, wherein a threshold of the secondtransistor is detected by (i) initializing the terminal potential of thelight-emitting element and turning off the third transistor and (ii)subsequently, while the predetermined electric potential keeps beingsupplied to the control terminal of the second transistor, turning thesecond transistor from an on-state to an off-state under a conditionwhich allows no electric current to flow through the light-emittingelement.
 14. The display device as set forth in claim 13, wherein a datasignal potential is written from the data line into the control terminalof the second transistor via the fourth transistor, after (i) thethreshold of the second transistor is detected and (ii) the firsttransistor is turned off.
 15. The display device as set forth in claim14, wherein, after the data signal potential is written into the controlterminal of the second transistor, the first transistor is turned on, sothat an electric current is caused to flow from the first power sourceline to the light-emitting element, via the first transistor and thesecond transistor.